The pre invention is directed to a structure for a MOS-gated semiconductor device that increases the size of the active current-carrying area of the device relative to the device's contact areas, and more particularly to a mesh structure for a wafer used in a MOS-gated semiconductor device that relatively increases the size of the channel and neck regions and decreases the size of the source contact regions.
Known power MOSFET's may comprise a multiplicity of individual cells that may be electrically connected in parallel. The cells are typically small; for example, each cell may be about twenty-five microns in width so that tens of thousands may be formed on a single silicon wafer on the order of 300 mils square. A number of geometric arrangements for the unit cells are possible, including elongated strips.
In power MOSFET's, it is known to form such devices by a double diffusion technique which begins with a common drain region of, for example, N conductivity type material, that is formed on a N+ conductivity type substrate. Within the drain region, a base region is formed by means of a first diffusion to introduce impurities of one type, and then a source region is formed entirely within the base region by means of a second diffusion to introduce impurities of the opposite type. If the drain region is N type, then the first diffusion is done with acceptor impurities to produce a P type base region, and the second diffusion is done with donor impurities to produce a N+ type source region. At the drain region surface, the base region exists as a band between the source and drain regions.
Conductive gate electrodes are formed on the surface over the base region band and separated by a gate insulating layer to define an insulated gate electrode structure. When voltage of a proper polarity is applied to the gate electrodes during operation, an electric field extends through the gate insulating layer into the base region inducing a conductive channel just under surface. Current flows horizontally between the source and drain region through the conductive channel.
With reference now to FIG. 1, known MOS-gated semiconductor devices may include a multi-layer wafer 12 overlain with a gate 14 and source metal 16. For example, in a metal oxide semiconductor field effect transistor (MOSFET) the layers may include an N+ substrate 18, an N- voltage supporting layer 20, a body region 22 implanted in the voltage supporting layer 20, and an N+ source region 24 implanted in the body region 22. As may be seen in FIG. 1, the body regions 22 and source regions 24 may form cells separated by portions of the voltage supporting layer 20. The region between the cells near the surface of the wafer is known as the neck region 26 and the region between the source region and the neck region near the surface of the wafer is known as the channel region 28. The channel region 28 and the neck region 26 are the active current-carrying areas of the device.
Various patterns for the MOS-gated device's cellular structure are known in the art. A hex geometry pattern is illustrated in FIG. 1, a stripe geometry pattern is illustrated in FIG. 2 and an atomic lattice pattern is illustrated in FIG. 3. It may be seen that a wafer 12 for a MOS-gated semiconductor device often includes a vertical cross section showing the cellular structure (for example, as seen on the left-hand face of the vertical cross sections of FIGS. 1-3). Note that other cross sections (for example, the right-hand face of the vertical cross sections of FIGS. 2-3) may not include the cellular structure.
To increase the current-carrying capability of a MOS-gated semiconductor device, it is desirable to increase the current-carrying area per unit area of device. With reference to FIGS. 1-3, one of the regions that takes up current-carrying area is the region in the center of each cell or stripe that is contacted by the source metal 16. This region is known as the source contact region 30.
One method by which the current carrying area can be increased is to reduce the area at the top surface of the chip utilized by the source contact area. This reduction must be made, if at all, while (a) providing sufficient source contacts; (b) maintaining an upper surface structure which permits ready access to the source contact area and to the distribution of gate voltage over the channel regions; and (c) maintaining or improving the amount of channel area; all while maintaining a topography which is readily manufacturable.
Accordingly, it is an object of the present invention to reduce the size of the source contact region relative to the size of the active current-carrying area of the device, while maintaining the cellular structure of MOS-gated devices.
It is a further object of the present invention to provide a novel pattern for a wafer used in a MOS-gated semiconductor device in which the pattern includes an array of ribbons extending linearly from a source contact region, each of the ribbons having a single source region between two channel regions.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of preferred embodiments.